This application is related to Japanese application No. 2000-102359 filed on Apr. 4, 2000, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
This invention relates to a semiconductor device having an SOI structure, and more particularly to a semiconductor device of SOI structure in which a xe2x80x9ckink effectxe2x80x9d is reduced.
2. Description of the Related Art
A MOSFET fabricated on a generally known SOI substrate such as SOS, SIMOX or BSOI substrate, is capable of a low-voltage and high-speed operation. Besides, the SOI MOSFET has the advantage of realizing a smaller layout area, as compared with a device fabricated on a bulk silicon substrate.
Meanwhile, whereas a bulk silicon MOSFET has four terminals (gate, drain, source and substrate), the SOI MOSFET has only three terminals (gate, drain and source). Therefore, the SOI MOSFET deteriorates the electrical characteristics of a device, especially a short channel effect, a breakdown voltage between drain/source, etc.
More specifically, in the bulk silicon MOSFET, as shown in FIGS. 7(a) and 7(b), a parasitic bipolar (NPN) transistor has its base fixed to the substrate, and the substrate-source junction of the MOSFET is reverse biased. Therefore, even when an impact ionization current Ii is generated in the vicinity of the drain region of the MOSFET, the parasitic bipolar transistor hardly affects the operation of the MOSFET.
On the other hand, in the SOI MOSFET, as shown in FIGS. 8(a) and 8(b), a parasitic bipolar transistor has its base formed of a surface semiconductor layer in a floating state. In the ordinary operation of the MOSFET, therefore, an impact ionization current Ii generated in the vicinity of the drain region of the MOSFET acts as the base current of the parasitic bipolar transistor and gives rise to a positive feedback effect, with the result that the deterioration of a short channel effect and the reduction of a breakdown voltage between drain/source are brought about. Besides, in a case where the channel region of the MOSFET is formed as a comparatively thick surface semiconductor layer, the operation thereof becomes a partially depleted mode, and a so-called xe2x80x9ckink effectxe2x80x9d appears in the output characteristics thereof due to impact ionization, so that SOI MOSFET characteristics are drastically limited.
FIGS. 9(a) and 9(b) are graphs illustrative of the characteristics of the ordinary SOI MOSFET having the floating body, in which the relationships between a subthreshold current Id and a gate voltage Vg are shown in FIG. 9(a), while the relationships between an output current Id and a drain-source voltage Vd are shown in FIG. 9(b). By the way, the example of this SOI transistor had gate length L=0.35 xcexcm, channel width W=10 xcexcm, thickness of a gate oxide film=7 nm, thickness of a surface silicon body layer=50 nm and thickness of a buried insulating film=120 nm. Besides, in applications to LSIs driven by low voltages, a standby current limits the battery life of a portable system, and it is determined by the transistor current at Vg=0 V.
The kink effect ascribable to the impact ionization is observed for the drain voltage Vd greater than Vdk. In this case, the kink starting voltage Vdk is about 0.9 V.
Excess majority carriers (holes for an NMOSFET) ascribable to the impact ionization raise the potential of the floating body and cause the kink effect in the I-V characteristic.
The rise of the body potential decreases a threshold voltage, and it is observed as the decrease of a subthreshold swing (S factor) in the Id-Vg characteristic shown in FIG. 9(a). More specifically, S=85 mV/dec holds for Vd=0.1 V and S=35 mV/dec holds for Vd=1.5 V (Vd greater than Vdk). This is based on the accumulation of the excess majority carriers in the SOI substrate.
In general, the kink effect depends upon the impact ionization, the lifetime of carriers in the body, etc. and is therefore difficult of prediction and control. Moreover, the kink effect incurs the large fluctuations of device characteristics, especially an undesirable standby leakage current in a device of low-voltage operation.
In order to cope with the drawbacks, various methods have been proposed as exemplified below. It is the present situation, however, that any of the methods has not yet succeeded in efficiently preventing the kink effect without deteriorating the various characteristics of the SOI MOSFET.
(1) An SOI MOSFET is so constructed that a channel region is formed of a low-concentration of impurity and thin surface semiconductor layer which is fully depleted. Thus, the SOI MOSFET of full depletion mode can be obtained, and the kink effect can be theoretically prevented.
For the purpose of actually preventing the kink effect in the full depletion mode SOI MOSFET, it is necessary to set an impurity concentration considerably lower than 1xc3x971017 cmxe2x88x923 and a low threshold voltage of about 0.1 V, in the case of employing a surface semiconductor layer 50 nm thick by way of example. On this occasion, however, the OFF leakage current of the MOSFET increases.
(2) As shown in FIG. 10 by way of example, an SOI MOSFET is constructed on an active region 11 of constricted shape, and body contacts 13 are formed in the active region 11 (refer to the official gazette of Japanese Patent Application Laid-open No. 8431/1996). Thus, a channel region formed of a comparatively thick surface semiconductor layer can be held at a fixed potential, so that a floating body effect and a parasitic bipolar effect can be suppressed as in a device employing bulk silicon.
In the case of fixing the potential of the channel region, however, the occupation area of the body contacts 13 is required, resulting in an increased element area. Besides, in a case where the surface semiconductor layer has been fully depleted, the suppressions of the floating body effect and the parasitic bipolar effect are nullified. Further, when the potential of the channel region is fixed, a back-gate effect and a drain junction capacitance are increased to degrade the quality of a device.
(3) As shown in FIG. 11 by way of example, two SOI MOSFETs are connected in series so as to share a drain 14 in an electrically floating state (refer to the official gazette of Japanese Patent Application Laid-open No. 218425/1993).
It is difficult, however, to realize the SOI MOSFETs for a device which has a channel length of subhalfmicron order. For example, in a device having a gate length of 0.35 xcexcm, the channel length d of each of P-type regions 15, 16 becomes about 0.1 xcexcm. This length is substantially equal to a lateral diffusion length in an N+ impurity diffused layer. It is therefore extraordinarily difficult to control the impurity diffusion of the diffused layer. Moreover, when the channel length d is about 0.1 xcexcm, a depletion layer region extending from the drain region 14 punchs through the whole channel region 16. It is therefore very difficult to control the characteristics of the device.
(4) As shown in FIG. 12, an SOI MOSFET is constructed using a surface silicon layer 20 made of single-crystal silicon of N-type, and its surface channel 21 is set with P-type (refer to the official gazette of Japanese Patent Application Laid-open No. 13376/1987). Owing to this structure, holes generated by impact ionization are recombined in the N-type surface silicon layer 20, so that a kink effect can be suppressed. Besides, a source-drain leakage current can be suppressed by fully depleting the surface silicon layer 20 in the OFF state of the MOSFET.
This structure, however, has the problems that a short channel effect and punchthrough are liable to occur, and that a subchannel leakage is caused by the short channel effect.
(5) As shown in FIG. 13, an SOI MOSFET is fabricated into a structure which has an N-type region 31 at a middle channel part in a surface silicon layer 30 (refer to the official gazette of Japanese Patent Application Laid-open No. 30371/1991). Thus, the withstand voltage of the MOSFET can be enhanced.
However, even when each of two channel regions 32, 33 separated by the N-type region 31 is formed as the minimum channel region, it requires a large layout area and incurs degradation in the current driving capability of the transistor.
(6) Further, as shown in FIG. 14, an SOI MOSFET is fabricated into a structure which has an impurity region 41 under a source 40 (refer to the official gazette of Japanese Patent Application Laid-open No. 43475/1986). Thus, the lifetime of carriers accumulated in a surface semiconductor layer 42 can be shortened, with the result that a kink effect can be suppressed.
With this structure, however, a process margin for forming the impurity region 41 in a very thin surface semiconductor layer (thinner than about 50 nm), which is required of, for example, a full depletion mode device having a gate length of 0.25 xcexcm, is very narrow to incur the complication of a manufacturing process and the lowering of an available percentage.
The present invention has been made in view of the problems explained above, and has for its object to provide a semiconductor device of SOI structure which can suppress a kink effect arising in a surface semiconductor layer of floating state, without degrading the various characteristics mentioned above and without contradicting the microfabrication of the device.
According to the present invention, provided a semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.